Jevons paradox is lazy analysis: Evaluating the risk of AI overbuilding

i think the author and most analysts miss one important bottleneck.

If you look at chip wafer volume from TSMC, they've increased their capacity by a "whopping" 20% since 2020 to 2025. Yes, that's right. All this talk about overcapacity and TSMC has only managed to increase total chip volume by 20% in 5 years.

We're capped ASML and TSMC. No amount of math finesse can get around it. It's bottlenecked at the very top.

Even if Silicon Valley wants 10x number of chips, they can't. This buildout is physically capped by two behemoths.